In recent years, various three dimensional integrated circuit devices have been proposed to meet the increasing need for higher density integrated circuits. Attempts to fabricate MOSFET devices stacked on the top of bulk silicon MOSFETs include the recrystallization of a polycrystalline silicon layer formed over the bulk silicon MOSFET. Typically, the recrystallization procedure would include a heat treatment for a period of one hour or more at a temperature exceeding about 950.degree. C. Such a procedure may cause excessive diffusion of the N.sup.+ and P.sup.+ regions of the bulk MOSFETs compromising the potential performance of VLSI circuit devices fabricated in this way. Additionally, prior art stacked MOSFET structures contain substantial unwanted parasitic capacitance due to gate overlap with the source and drain regions.
What is needed is a structure and method of making that avoid the need for a high temperature, long duration heat treatment and result in reduced parasitic capacitance due to source/drain and gate overlap.